The storage device interfaces are demanded with more versatility, larger capability and higher transfer rate. For example, an IDE interface (officially called the ATA interface) is developed to support CD-RW, Zip other then hard disk drive. The earliest ATA interface has transfer rate of 16 MBps and is then improved to ATA 33 standard with 33 MBps, ATA 66 with 66 MBps and to ATA 100 and ATA 133 standard. However, the conventional ATA cable is a 40-conducior ribbon cable carrying signals between a motherboard and a hard disk driver. To maximize signal integrity and eliminate potential timing and noise problem, the cable should not be longer than 0.46 meter (18 inches). The cable with large amount of parallel conductors also cause serious electromagnetic interference (EMI) problem.
To overcome above drawbacks, a solution is a new ATA interface called serial ATA (SATA) interface, which uses four signal lines for data transmission and supports existing ATA and ATAPI devices. The serial ATA standard specification includes serial ATA types SATA I with 1.5 GHz bus speed, SATA II with 3 GHz bus speed and SATA III with 6 GHz bus speed, thus greatly enhancing transfer rate even with serial data transmission.
However, the transition from parallel ATA interface to serial ATA interface is gradual one, and during the transition the parallel ATA capability will continue to be available. Therefore, the present computer system can support both parallel ATA interface to serial ATA interface.
FIG. 1 shows a prior art physical layer apparatus for these two ATA interfaces (serial ATA and parallel ATA). The physical layer apparatus comprises a serial ATA physical layer 123 in a media access controller 121 of an I/O controller chip 12 (such as a south bridge chip). The media access controller 121 is connected to a serial ATA device 16 (such as serial ATA hard disk drive) through the serial ATA physical layer 123, and connected to a parallel ATA device 18 (such as a parallel ATA hard disk drive) through an IDE bus 14. The above-mentioned architecture can support both serial and parallel ATA devices. However, the serial ATA physical layer 123 is generally implemented with high-frequency analog circuit having larger occupied area. As a result, the I/O controller chip 12 will have excessively large area and the yield thereof is influenced.
Alternatively, the serial ATA physical layer apparatus may be separated with the media access controller, i.e., provided externally to the media access controller. FIG. 2 shows another feasible architecture of the physical layer apparatus for ATA interface. The I/O controller chip 22 has a media access controller 221 accessing a parallel ATA device 28 through an IDE bus 24. The media access controller 221 accesses a serial ATA device 26 through a serial ATA physical layer 261. More particularly, the serial ATA physical layer 261 is often directly connected to the IDE bus 24 for saving pin count of the I/O controller chip 22. This limits the accessing choice of the I/O controller chip 22 to one of the parallel ATA device and the serial ATA device. It is also inconvenient for user to choose peripheral device at his disposal.